The FET is a three terminal device like the BJT, but operates by a different principle. The three terminals are called the source, drain and gate. The voltage applied to the gate controls the current flowing in the source-drain channel. Because no current flows through the gate, the input impedance of the FET is extremely large (in the range of 1010 - 1015 Ω). The large input impedance of the FET makes them an excellent choice for amplifier inputs.
FET Schematic Symbols: -
Two Versions of the symbols are in common use. The symbols in the top row depict the source and drain as being symmetric. This is not generally true. Slight asymmetries are built into the channel during manufacturing which optimize the performance of the FET. Thus it is necessary to distinguish the source from the drain. In this class we will use the asymmetric symbols found on the bottom row, which depict the gate nearly opposite the source. The designation n-channel means that the channel is n doped and the gate is p doped. The p-channel is complement of n-channel.