Tuesday, December 9, 2008
Cut-off region: -
The transistor is off. There is no conduction between the collector and the emitter.(IB=0 therefore Ic=0)
Active region: -
The transistor is on. The collector current is proportional to and controlled by the base current (Ic=ßIB) and relatively insensitive to VCE. In this region the transistor can be an amplifier.
Saturation region: -
Saturday, December 6, 2008
The simple source follower is shown below. The improved version is shown at the right. The lower JFET forms a current source. The result is that VGS is held constant, removing the defects of the simple circuit.
For the on state the gate voltage VGS = 0 and for the off state |VGS| > |VGS.off| (of greater magnitude then VGS.off and with the same sign). The sign of the voltage depends on the type of FET, negative for n-channel and positive for p-channel.
Tuesday, December 2, 2008
Cut-off Region: -
The transistor is off. There is no conduction between the drain and the source when the gate-source voltage is greater than the cut-off voltage (ID = 0 for VGS > VGSoff)
The transistor is on. The drain current is controlled by the gate-source voltage (VGS) and relatively insensitive to VDS. In this region the transistor can be an amplifier.
In the active Region ID = IDSS (1 – VGS / VGSoff) 2
Ohmic Region: -
The transistor is on, but behaves as a voltage proportional to the source-drain voltage and is controlled by the gate voltage.
ID = IDSS [ 2 (1 – VGS / VGSoff) VDS / - VGSoff - (VDS / VGSoff) 2 ]
In the Ohmic Region: RDS ≈ VGSoff / 2IDSS (VGS - VGSoff) = 1 / gm
The FET is a three terminal device like the BJT, but operates by a different principle. The three terminals are called the source, drain and gate. The voltage applied to the gate controls the current flowing in the source-drain channel. Because no current flows through the gate, the input impedance of the FET is extremely large (in the range of 1010 - 1015 Ω). The large input impedance of the FET makes them an excellent choice for amplifier inputs.
FET Schematic Symbols: -
Two Versions of the symbols are in common use. The symbols in the top row depict the source and drain as being symmetric. This is not generally true. Slight asymmetries are built into the channel during manufacturing which optimize the performance of the FET. Thus it is necessary to distinguish the source from the drain. In this class we will use the asymmetric symbols found on the bottom row, which depict the gate nearly opposite the source. The designation n-channel means that the channel is n doped and the gate is p doped. The p-channel is complement of n-channel.